1. Field of the invention
The present invention relates to a character and graphic display device for displaying information received from a central processing unit, and more particularly it relates to a drive circuit for a character and graphic display device wherein a data memory of the central processing unit (CPU) and a display memory of the display device are common, that is, the display memory is located in a memory space of the CPU.
2. Description of the Prior Art
In recent years, as the semiconductor technology has been developed, small scale computers including programmable arithmetic unit LSI's, called microcomputers, have been marketed with a relatively inexpensive price. Those computers usually have keyboards as input devices and CRT display devices as output devices. In order to achieve a low price, various improvements have been made to memory units and the display devices serving as the output devices, which are apt to be expensive.
Home television receiver sets or those one with portions thereof (e.g. tuners) being eliminated may be used as the CRT display devices. Those CRT devices, however, have a low CRT afterglow property and have no memory function by themselves. Accordingly, a display memory for storing all of the codes of characters and/or graphic patterns to be displayed on a display screen is necessary. The CPU controls the data transfer to the display memory. The display memory is usually located in one of the following two ways;
In one way, the whole unit including the display memory is considered as an I/O device, and in the other way the display memory is located in the computer and addressed in the same manner as the data memory is addressed. The latter has been frequently used in the microcomputer system because of simplicity of read/write operation to the display memory. This technique is shown, for example, in the Japanese periodical "Transistor Gijutsu" May 1977, pages 215-217 and implemented in the commercially available Hitachi microcomputer MB 6880 L2.
FIG. 1 is a block diagram showing an example of a circuit construction of a prior art character and graphic display device. It comprises a memory (ROM) 2 for storing a computer system program, a memory (RAM) 6 for temporarily storing data when the system operates, a display drive circuit 7 for generating signals to display characters and/or graphic patterns on a CRT display device, not shown, a CPU 1 for controlling the units described above and processing data, a clock signal generator 4 for generating clock signals to be supplied to the CPU 1 based on basic clock signals from an oscillator 3, a timing signal generator 8 for generating timing signals for displaying characters and/or graphic patterns, and a switching circuit 5 for alternately switching the timing signals for the timing signal generator 8 and addressing signals for addressing data from the CPU 1 to the RAM 6 to selectively supply those signals to the RAM 6. Numeral 9 denotes a data bus, numeral 10 denotes an address bus, numeral 11 denotes a timing signal path and numeral 12 denotes a video signal output terminal which leads to the CRT display device (which is usually a separate box from a box including the CPU).
The system shown in FIG. 1 is a character and graphic display device which utilizes a display mode called .phi..sub.2 cycle steal display mode which enables continuous display of characters and/or graphic patterns on the display screen of the display device. This mode is also referred to as a cycle-steal-mode DMA (Direct Memory Access) or a transparent memory system.
As shown in FIG. 2, in the .phi..sub.2 cycle steal display mode, the operation of the CPU 1 is based on the fact that the address signal (FIG. 2(c)) is issued T.sub.1 time period later than the leading edge of .phi..sub.2 clock signal (FIG. 2(a)) and data signal (FIG. 2(d)) is accessed at the trailing edge of .phi..sub.2 clock signal (FIG. 2(b)). During the absence of the .phi..sub.2 clock signal b, that is, in the time period T.sub.2, the RAM 6 is disconnected from the address bus 10 of the CPU 1 and the display address signal is transmitted through the timing signal path 11 from the timing signal generator 8 to receive data from the RAM 6 for displaying the characters and/or graphic patterns.
The operation of the circuit of FIG. 1 is now explained for an example where characters are displayed on the display device, not shown, in accordance with a program stored in the ROM 2.
The CPU 1 fetches character data to be displayed in an internal register of the CPU 1 in accordance with the program stored in the ROM 2 which is addressed by the addressing signals. The CPU 1 then produces an address signal for a display area of the RAM 6 which corresponds to a character display position on the display device, and the prefetched character data signal. The switching circuit 5 is switched by the .phi..sub.2 clock signal b so that the CPU 1 and the RAM 6 are connected together during a time period T.sub.3 of the .phi..sub.2 clock signal, as shown in FIG. 2. Thus, the CPU 1 writes the character data signal into the RAM 6 during the time period T.sub.3. In this manner, the character data signals are sequentially written into the RAM 6 during the time period T.sub.3. As shown in FIG. 2, the switching circuit 5 is switched to the position opposite to that shown in FIG. 1, during time period T.sub.2 of the .phi..sub.2 clock signal so that the timing signal generator 8 is connected to the RAM 6 through the signal path 11. Accordingly, the character data signals stored in the RAM 6 are sequentially read out during the time period T.sub.2 by the display address signals from the timing signal generator 8 and they are taken from the video signal output terminal 12 as the character/graphic pattern display signals via the character/graphic pattern display drive circuit 7 and displayed on the CRT display device not shown. In this manner, the switching circuit 5 is switched by the .phi..sub.2 clock signal b so that the write operation of character data from the CPU 1 to the RAM 6 and the read operation of the character data from the RAM 6 by the display address signal from the timing signal generator 8 are effected in one character display period T.sub.4, as shown in FIG. 2(e). The adoption of the .phi..sub.2 cycle steal mode provides the following advantages:
(1) The characters can be continuously displayed on the CRT display screen while the CPU continuously reads and writes the RAM which stores the display data. (This RAM may hereinafter be referred to as display RAM.)
(2) Since the display RAM is continuously read during the time period T.sub.2 of the .phi..sub.2 clock signal shown in FIG. 2 by the display address signal from the character display timing signal generator, a dynamic RAM which is much less expensive than a static RAM may be used without adding a refresh counter.
In this .phi..sub.2 cycle steal mode, however, since one-character data read during the time period T.sub.2 of the .phi..sub.2 clock signal shown in FIG. 2 is displayed for one character display period T.sub.4 (FIG. 2(e)) or one CPU clock period, the number N of characters that can be displayed horizontally when the clock signals appear at 1 MH.sub.Z which is an upper limit of an operation speed of a conventional CPU (a synchronous bus type microprocessing unit) would be 64 (N=64 .mu.s/T.sub.4) assuming that one horizontal scan period for the CRT display is 64.mu. seconds. This is the number of characters that can be displayed in one horizontal scan period including blanking periods. Assuming that approximately 70% of it is available for the actual display, the number of characters that can be actually displayed on the display screen is at most 45 (N=64.times.0.7). This is not sufficient for the display of multiple digits resulting from complex arithmetic operations or the display of tabulation of multiple items for business use.
One of the most conventional methods for increasing the number of characters per line displayed on the display device is to increase the clock frequency for operating the CPU. This method, however, needs a high speed CPU which is more expensive. In addition to the CPU, the RAM 6 also needs to operate at high speed. It is expensive and special. As an example, in order to increase the number of characters displayed per horizontal line to 120, the one character display period T.sub.4 is to be equal to 530 ns (=64 .mu.s/120 characters). The CPU clock frequency f.sub..phi. when T.sub.4 =530 ns is 1.88 MH.sub.Z (=1/T.sub.4), which requires a high speed CPU operable with 2 MH.sub.Z clock signals. The time period T.sub.2 required to read the RAM 6 is approximately equal to T.sub.4 /2, that is, it is 265 ns (=530/2). The time period (cycle time) required to read out conventional dynamic RAM is 320 ns-375 ns, which does not meet the readout time requirement mentioned above. Accordingly, the conventional dynamic RAM cannot be used.